1. Field of the Invention
This invention relates to an electrically rewritable and non-volatile semiconductor memory device, specifically to a high-speed data write method thereof.
2. Description of the Related Art
A NAND-type flash memory is known as one of electrically erasable and programmable ROMs (EEPROMs). This flash memory has a memory cell structure with a small unit cell area of about 4F2 (F: minimum device feature size), thereby leading other EEPROMs in miniaturization and capacity. In case a multi-value or multi-level data storage scheme is adapted to this memory, in which a memory cell stores two or more bits, the capacity may be increased double or more without increasing the chip area.
The NAND-type flash memory is currently adapted to a non-volatile data storage media in various mobile apparatuses. In these applications, it is required of the flash memory to be not only increased in capacity but also improved in access speed. At present, the access speed of the data storage media is strongly influenced by that of the NAND-flash memory. Therefore, it is a problem how to improve the programming throughput of this flash memory.
Data program or write of the NAND-type flash memory is performed with an FN tunneling current. To control data write thereof, it is used such a method that a write pulse application operation and a write-verify operation followed it are repeatedly performed with stepping-up the write pulse voltage. In this method, a write time will be substantially determined based on a difference of the amount of threshold shift between higher write speed cells and lower write speed ones and the voltage step width of the write pulse.
The detail will be explained below. The number of write cycles, which is necessary for writing a desired threshold voltage, is obtained by dividing a threshold voltage distribution obtained with one write pulse application, which expresses write speed differences among cells, by a voltage step of the write pulse, and the write time is proportional to about the number of write cycles. In case of a binary data storage scheme, only one mode of the threshold voltage shift from an erase state to a write data state is used. Therefore, the threshold voltage range, which is permissible to the write data state, is so wide that it is permissible to write data with a relatively large voltage step.
By contrast to this, in case of a multi-level data storage scheme, for example, four-level data storage scheme, it is in need of writing three data states from an erase state. Therefore, a threshold voltage range assigned to a write data state becomes narrower. This leads to need of writing data in such a manner as to shift a data threshold voltage little by little with a small voltage step width. As a result, the number of write cycles becomes larger, and the write time becomes longer in comparison with those in the binary data storage scheme.
Further, a capacitive coupling noise between adjacent cells (especially between adjacent floating gates), which is increased in accordance with the design rule shrink, becomes a material cause for preventing the flash memory from being writable at a high speed. Specifically, in the four-level data storage scheme, it is in need of setting each gap between data threshold distributions to be narrower in comparison with that in the binary data storage scheme, so that the above-described capacitive coupling noise strongly influences on the write speed. To reduce the influence of the capacitive coupling, it is required in general to make the write voltage step small.
There have already been provided various write speed-up techniques in the conventional flash memories, specifically ones with a multi-level data storage scheme, one of which is, for example, as follows: data write is performed with a large voltage step until a certain verify-level, which is set to be a little lower than a target write threshold voltage, and thereafter performed with a reduced amount of the threshold voltage shift, thereby substantially improving the write speed (for example, refer to Unexamined Japanese Patent Application Publication No. 2003-196988). To suppress the threshold voltage shift amount in the latter half of the write sequence, the bit line voltage is slightly raised so as to decrease the voltage difference between the word line and the channel of the memory cell.
Other techniques have been provided as follows: one technique is to improve the data write speed with such a write method as possible to reduce the influence on the data threshold voltage variation due to capacitive coupling between cells (for example, refer to Unexamined Japanese Patent Application Publication No. 2004-192789); and another technique is, for the purpose of making the data threshold voltage distribution narrow or shortening the write time, to measure the memory cells' threshold voltages before or after the initial write signal, and determine the following write conditions based on the measured result (for example, refer to Unexamined Japanese Patent Application Publication No. 2000-113686).